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This paper describes a radar architecture utilising bandpass sampling techniques suitable for high resolution random stepped frequency radar systems with multiple channels. The architecture has advantages with respect to increased flexibility and low-cost implementation in hardware with associated benefit of reducing sampling frequency of the ADC, suitable for integrated systems-on-a-chip. © 2012 IEEE.

Original publication

DOI

10.1109/RADAR.2012.6212192

Type

Conference paper

Publication Date

30/07/2012

Pages

0499 - 0503