A 65mW 1.2Gsamples/s 6-bit flash ADC in 0.13μm CMOS
Wang K., Skafidas E., Evans R.
This paper presents a high-speed low-power flash analog-to-digital converter designed and optimized in a 0.13μm CMOS technology. The design consideration and optimization techniques used in each block are discussed specifically. The simulation result shows that the ADC consumes 65mW with a supply voltage of 1.2V at 1.2G samples per second. The figure of merit shows 1.3pJ per conversion step. The simulation result of the full flash ADC shows improvement in nonlinearity and power dissipation compared to work previously described in the literature.