A 7GHz 1mV-input-resolution comparator with 40mV-input-referred-offset compensation capability in 65nm CMOS
Huynh AT., Ta CM., Nadagouda P., Evans RJ., Skafidas E.
A 7GHz-clock 1mV-input-resolution comparator is designed and simulated in a 65nm CMOS process. The comparator offset is compensated by changing the body voltages of the input differential triple-well NFET transistor pair. A reset switch is added between two regeneration nodes to further match voltages in reset phase. Kickback noise in this comparator is reduced by isolating regeneration nodes of the cross-coupled inverters from the input nodes. Simulated delay of the comparator at Vin 1mV@VDD1.2V is 69ps. The comparator can operate with a 7GHz clock and a differential input voltage as small as 1mV@VDD1.2V and can compensate for an input-referred offset of up to 40mV. © 2011 IEEE.