Cookies on this website

We use cookies to ensure that we give you the best experience on our website. If you click 'Accept all cookies' we'll assume that you are happy to receive all cookies and you won't see this message again. If you click 'Reject all non-essential cookies' only necessary cookies providing core functionality such as security, network management, and accessibility will be enabled. Click 'Find out more' for information on how to change your cookie settings.

A variable delay line (VDL) is designed on a 130-nm CMOS process. Post-layout simulation results show that the VDL has a phase tuning range of 100 degrees at 60 GHz. It exhibits a wideband matching to 50-Ohm terminations from 20 GHz up to exceeding 80 GHz. The group delay variation is less than 4 ps within a bandwidth of 10 GHz. At its maximum phase shift, the VDL introduces a loss of 6 dB. The design features a small footprint of 430 μm × 220 μm and can be easily extended to provide wider phase tuning range. © 2008 IEEE.

Original publication

DOI

10.1109/CCECE.2008.4564877

Type

Conference paper

Publication Date

22/09/2008

Pages

1915 - 1917